杰平方定律（J?Square's?Law）： 碳化硅功率芯片性能提升與成本降低的創(chuàng)新之路?

引言

在快速演進的電力電子領域，碳化硅功率芯片正憑借其高效率、高功率密度及卓越的高溫穩(wěn)定性等核心優(yōu)勢，逐步取代傳統(tǒng)硅基器件，成為推動產(chǎn)業(yè)變革的關(guān)鍵力量。作為電動汽車、可再生能源、工業(yè)自動化及人工智能等前沿領域的核心組件，碳化硅芯片是實現(xiàn)高效電力傳輸?shù)幕?。然而，其高昂的制造成本與工藝復雜性，長期以來制約著該技術(shù)的廣泛應用。為突破這一瓶頸，杰平方半導體（上海）有限公司（下稱“杰平方半導體”）創(chuàng)新性地提出了“杰平方定律”（J Square's Law）：通過持續(xù)的技術(shù)革新與成本優(yōu)化，致力于每兩年將碳化硅功率芯片的“價值”翻倍。這一定律不僅為碳化硅技術(shù)的發(fā)展擘畫了清晰藍圖，也為終端用戶創(chuàng)造了切實可觀的商業(yè)價值。

“杰平方定律”并非憑空設想，而是植根于對一系列關(guān)鍵性能指標的深度考量，以及對碳化硅MOSFET核心成本驅(qū)動因素的系統(tǒng)性剖析。杰平方半導體通過精準攻克這些技術(shù)瓶頸，致力于實現(xiàn)性能提升與成本下降的協(xié)同優(yōu)化，從而有力推動碳化硅技術(shù)的商業(yè)化進程。

“杰平方定律”的三大核心支柱

“杰平方定律”的實現(xiàn)，依賴于對三大關(guān)鍵領域的系統(tǒng)性優(yōu)化，這些領域共同構(gòu)成了提升碳化硅功率芯片價值的核心支柱。

（一）顯著降低導通電阻

導通電阻是衡量功率器件性能的核心參數(shù)，其降低直接關(guān)聯(lián)到芯片功耗的減少與能源效率的提升。杰平方半導體通過多項創(chuàng)新舉措，有效降低了Rdson：

• 優(yōu)化碳化硅表面處理與氧化層技術(shù)：通過精確控制碳化硅/二氧化硅（SiO?）界面處理工藝，有效減少了界面陷阱（DiT）和近界面氧化物陷阱（Niot），顯著提升了溝道遷移率并增強了柵氧化層的長期可靠性。此外，氧化層的優(yōu)化使閾值電壓分布更加均勻，這對器件的穩(wěn)定性和一致性至關(guān)重要。
• 創(chuàng)新器件結(jié)構(gòu)設計與精確仿真：公司引入了先進的器件設計理念，如超結(jié)結(jié)構(gòu)與背面減薄技術(shù)。這些結(jié)構(gòu)創(chuàng)新與精確的仿真技術(shù)相結(jié)合，使器件在保持高擊穿電壓的同時，實現(xiàn)了更低的導通電阻。超結(jié)結(jié)構(gòu)通過在漂移區(qū)引入交替的P型和N型區(qū)域，有效提高了器件的擊穿電壓并降低了比導通電阻；背面減薄技術(shù)則有助于降低襯底電阻，進一步優(yōu)化了整體器件性能。

（二）有效減小芯片面積

芯片面積是影響制造成本的關(guān)鍵因素。在保持性能的同時減小芯片面積，可以顯著降低單位芯片成本并提高晶圓產(chǎn)出。杰平方半導體減小面積的主要策略包括：

• 工藝流程的精細化優(yōu)化：通過精細縮小平面器件的元胞尺寸，并結(jié)合Contact溝槽結(jié)構(gòu)設計，實現(xiàn)了芯片面積的有效壓縮。更小的單元間距意味著在相同面積內(nèi)可以集成更多有源單元，從而提高電流密度；而溝槽結(jié)構(gòu)能更高效地利用芯片的垂直空間，進一步減小了器件尺寸。

（三）全面提高良率和可靠性

高良率和卓越的可靠性是碳化硅芯片實現(xiàn)大規(guī)模應用的基礎。杰平方半導體通過以下措施確保產(chǎn)品質(zhì)量和穩(wěn)定性：

• 嚴控原材料與關(guān)鍵工藝缺陷：對原材料進行嚴格篩選和進料檢驗，并對外延生長、光刻、沉積、刻蝕和研磨等關(guān)鍵工藝步驟進行實時監(jiān)控，以有效識別和預防潛在缺陷源，其中包括減少外延過程中導致器件失效的“殺手級缺陷”。
• 部署先進制造管理系統(tǒng)：公司已部署了包括配方管理系統(tǒng)、統(tǒng)計過程控制、高級過程控制、故障檢測與分類、批次間控制和人工智能在內(nèi)的先進制造執(zhí)行系統(tǒng)。這些系統(tǒng)的應用顯著提高了工藝的一致性和穩(wěn)定性，減少了生產(chǎn)中的變異性。
• 構(gòu)建全自動化生產(chǎn)線：公司已建成全自動化生產(chǎn)線，集成了設備自動化編程、自動化物料搬運系統(tǒng)和標準機械接口。自動化不僅大幅提升了生產(chǎn)效率、杜絕了人為失誤，還進一步保障了產(chǎn)品的高良率與高可靠性。

據(jù)代工廠數(shù)據(jù)顯示，杰平方半導體的代工晶圓產(chǎn)品良率，比同一代工廠其他客戶的同類產(chǎn)品高出約5%。

通過以上全面而系統(tǒng)的優(yōu)化措施，杰平方半導體不僅實現(xiàn)了關(guān)鍵技術(shù)的突破，更為碳化硅功率芯片的商業(yè)化成功奠定了堅實的基礎。

成本驅(qū)動因素與降本目標

為實現(xiàn)代際間50%的成本降低目標，杰平方半導體深入分析了碳化硅MOSFET制造中的關(guān)鍵成本驅(qū)動因素，并設定了明確的降本路徑。這些驅(qū)動因素主要包括：

• RSP (mOhm·cm²)：從G2到G3代，RSP已實現(xiàn)25%的實際降低；預計從G4到G6代，將平均降低15%至21%（具體數(shù)值因產(chǎn)品而異）。此優(yōu)化是在對擊穿電壓、臨界電場及遷移率等所有關(guān)鍵器件參數(shù)進行精細平衡后達成的。
• 襯底：6英寸碳化硅P-等級襯底是當前芯片制造成本的主要構(gòu)成部分之一。公司的目標是實現(xiàn)襯底成本同比降低14%。這主要得益于制造工藝的持續(xù)成熟與良率的穩(wěn)步提升。
• 外延：外延生長是另一關(guān)鍵且高成本的制造環(huán)節(jié)。通過工藝成熟度提升與技術(shù)創(chuàng)新，公司已實現(xiàn)外延成本同比降低11%-15%，并預計在未來1-2年內(nèi)將進一步下降。
• 晶圓制造成本：此項成本主要通過技術(shù)設計與工藝集成優(yōu)化來控制。例如，G3產(chǎn)品的光掩膜版數(shù)量已從平均12層少至10層。公司通過此類工藝流程優(yōu)化，目標實現(xiàn)年均5%或每兩年10%的成本削減。
• 封裝與最終測試：通過持續(xù)提升晶圓良率并擴大生產(chǎn)規(guī)模，封裝與最終測試環(huán)節(jié)的成本有望進一步降低5%。

通過對上述關(guān)鍵成本驅(qū)動因素的有效管控與持續(xù)優(yōu)化，杰平方半導體有信心為客戶實現(xiàn)產(chǎn)品價值的翻倍。這不僅彰顯了公司卓越的成本管控能力，也為碳化硅技術(shù)的大規(guī)模商業(yè)化應用奠定了堅實的經(jīng)濟基礎。

平面MOSFET的技術(shù)創(chuàng)新與優(yōu)化

杰平方半導體在平面MOSFET技術(shù)領域取得了一系列關(guān)鍵創(chuàng)新，這些創(chuàng)新對提升器件性能與降低成本至關(guān)重要。

以G3產(chǎn)品為例，其光罩層數(shù)已從平均12層精簡至10層，具體優(yōu)化措施包括：

• 精細化的元胞尺寸縮放：通過精密的設計與仿真，公司成功實現(xiàn)了代際間的單元間距持續(xù)縮小。此舉能夠在相同芯片面積內(nèi)集成更多晶體管，從而顯著提高電流密度，使終端客戶得以進一步縮小功率模塊的尺寸。
• 降低源極接觸電阻（Rcs）：在不影響其他關(guān)鍵性能的前提下，源極接觸電阻得到有效降低，從而為減小器件整體導通電阻做出了直接貢獻。
• 優(yōu)化溝道電阻（Rch）：降低溝道電阻是提升器件性能的核心。在優(yōu)化過程中，公司充分考量了漏致勢壘降低效應，在降低溝道電阻的同時，有效抑制了其對閾值電壓穩(wěn)定性及關(guān)態(tài)漏電流的負面影響。
• 改善SiO?/SiC界面質(zhì)量：通過優(yōu)化界面特性，顯著減少了界面態(tài)與電荷陷阱，從而提升了溝道遷移率。這不僅進一步降低了導通電阻，也全面提高了器件的效率與長期可靠性。
• 縮短JFET區(qū)寬度：適度縮短JFET區(qū)寬度有助于有效縮減芯片面積。值得一提的是，此優(yōu)化需嚴格控制在臨界限制之內(nèi)，以避免對器件性能產(chǎn)生不利影響。
• 優(yōu)化襯底電阻（Rsub）貢獻：采用先進的晶圓減薄技術(shù)，增加了導通電阻的設計裕量，進一步優(yōu)化了器件的整體性能表現(xiàn)。

這些系統(tǒng)性的技術(shù)創(chuàng)新，共同鞏固了杰平方半導體在碳化硅MOSFET領域的領先地位，使其能夠持續(xù)為客戶提供高性能、高性價比的解決方案。

“杰平方定律”與“歸一化成本趨勢”的對比及未來展望

自2023年正式實施以來，“杰平方定律”已取得顯著成效。展望未來，杰平方半導體將持續(xù)聚焦技術(shù)創(chuàng)新，并與核心襯底及外延供應商深化戰(zhàn)略合作，以驅(qū)動成本進一步降低、良率持續(xù)提升。該戰(zhàn)略規(guī)劃將延續(xù)至2030年，屆時預計將成為行業(yè)發(fā)展的關(guān)鍵轉(zhuǎn)折點——完成從6英寸向8英寸碳化硅襯底的歷史性過渡。

預計從2026年開始，杰平方半導體將“杰平方定律”的成功經(jīng)驗全面應用于8英寸碳化硅平臺的開發(fā)。這意味著，在成本可控的前提下，公司將為終端客戶提供近乎翻倍的芯片產(chǎn)出。此項戰(zhàn)略將貫穿6英寸與8英寸襯底的迭代與過渡期，并預計在2030年前完成。

這一前瞻性布局，不僅彰顯了杰平方半導體在技術(shù)路線圖上的清晰愿景與堅定執(zhí)行力，更預示著整個碳化硅功率芯片行業(yè)將邁向一個更高效率、更具成本效益的全新時代。

結(jié)論

“杰平方定律”，是杰平方半導體在碳化硅功率芯片領域銳意創(chuàng)新、追求卓越的集中體現(xiàn)。通過對導通電阻、芯片面積、良率與可靠性及制造成本進行系統(tǒng)性優(yōu)化，公司不僅顯著提升了碳化硅功率芯片的性能，更大幅降低了其制造成本。這一獨特的商業(yè)模式與技術(shù)戰(zhàn)略，確保了杰平方半導體能夠持續(xù)為客戶創(chuàng)造價值翻倍的產(chǎn)品，并在激烈的市場競爭中穩(wěn)固其領先地位。

展望未來，隨著“杰平方定律”的持續(xù)深化及向8英寸碳化硅襯底的平穩(wěn)過渡，杰平方半導體有望在未來幾年進一步鞏固其在全球碳化硅功率芯片行業(yè)的領導地位，并為全球電力電子產(chǎn)業(yè)的綠色、高效發(fā)展注入強勁動力。

因此，“杰平方定律”不僅是一項技術(shù)創(chuàng)新，更是一種有望引領行業(yè)的商業(yè)哲學。它將持續(xù)驅(qū)動碳化硅技術(shù)的演進，最終惠及全球廣大終端用戶，共創(chuàng)一個更高效、更可持續(xù)的未來。

附注：

• “杰平方定律”商標已由杰平方半導體（上海）有限公司于2023年在中國成功注冊。
• 所有權(quán)利歸杰平方半導體（上海）有限公司所有。本內(nèi)容受《中華人民共和國著作權(quán)法》及國際版權(quán)公約與條約保護。未經(jīng)書面授權(quán)，任何形式的復制、傳播或使用均屬嚴格禁止，違者將承擔相應法律責任。

以下為該文章的英文版：

J Square's Law: An Innovative Path to Enhanced Performance and Reduced Cost in SiC Power Chips

Introduction

In today's rapidly evolving power electronics landscape, Silicon Carbide (SiC) power chips are progressively replacing traditional silicon-based devices due to their superior performance advantages, such as high e?ciency, high power density, and excellent high-temperature stability. They have become core components in critical sectors like electric vehicles, renewable energy, industrial applications and artificial Intelligence (AI) for the power delivery efficiency. However, the manufacturing cost and complexity of SiC chips have historically posed challenges to their widespread adoption. To address this, J Square Semiconductor (Shanghai) Co., Ltd. has introduced and implemented "J Square's Law", aiming to double the value of SiC power chips every two years through continuous technological innovation and cost optimization. This forward-looking law not only sets a clear direction for SiC technology development but also delivers signi?cant value to end-users.

J Square's Law is not an arbitrary concept; it is built upon a series of key Figures of Merit (FOM) and thoroughly analyses of the core cost drivers in SiC MOSFET manufacturing. By systematically addressing these issues, J Square Semiconductor strives to ?nd the optimal balance between performance enhancement and cost reduction, thereby accelerating the commercialization process of SiC technology.

Core Pillars of J Square's Law

The realization of J Square's Law relies on optimizing several critical aspects, which collectively form the core pillars for enhancing the value of SiC power chips. These primarily include:

1.  Signi?cant Reduction in On-Resistance (Rdson)

On-resistance is a crucial parameter for power device performance, and its reduction directly correlates with chip power loss and improves energy e?ciency. J Square Semiconductor has adopted several innovative measures to reduce Rdson:

• Optimized SiC Surface Treatment and Oxide Layer Technology: Through precise control of the SiC/Silicon Dioxide (SiO2) interface treatment process, interface defects (DiT) and (Niot) are effectively reduced, signi?cantly improving channel mobility and enhanced the reliability of the gate oxide layer. Furthermore, optimization of the oxide layer leads to more uniform threshold voltage (Vth), which is vital for device stability and reliability.
• Innovative Device Structure Design and Precise Simulation: J Square Semiconductor has introduced advanced device design concepts such as Super Junction structures and Backside Thinning. These structural innovations, combined with precise simulation techniques, enable devices to achieve lower on-resistance while maintaining high breakdown voltage (BV). The super junction structure effectively increases the device's breakdown voltage and reduces speci?c on-resistance by introducing alternating P-type and N-type regions in the drift zone; backside thinning helps reduce substrate resistance, further optimizing overall device performance.

2. E?ective Reduction in Chip Area

Chip area is a key factor in?uencing manufacturing cost. Reducing chip area while maintaining performance can signi?cantly lower the cost per chip and increase the output per wafer. J Square Semiconductor's main strategies for area reduction include:

• Optimization of Individual Process Flows: By meticulously scaling down the cell pitch of Planar devices and incorporating contact trench structure designs, effective compression of chip area is achieved. Reduced planar device pitch means more cells can be integrated within the same area, increasing current density; trench structures more effectively utilize chip space, further reducing device size.

3. Comprehensive Improvement in Yield and Reliability

High yield and excellent reliability are fundamental for the large-scale application of SiC chips. J Square Semiconductor ensures product quality and stability through the following measures:

• Monitoring and Control of Incoming Material and Critical Process Defects: Strict screening and incoming inspection of raw materials, along with real-time monitoring of critical process steps such as Epitaxial (EPI) growth, lithography, deposition, etching and grinding, effectively identify and prevent potential defect sources. This includes reducing key Killer defects during the epitaxial process, which are primary causes of device failure.
• Implementation of Advanced Systems: Advanced manufacturing execution systems such as Recipe Management Systems (RMS), Statistical Process Control (SPC), Advanced Process Control (APC), and Fault Detection and Classi?cation (FDC), Run to Run (R2R) and Artificial Intelligent (AI) have been implemented. The application of these systems signi?cantly enhances process consistency and stability, reducing variability in production.
• Fully Automated Production Line: A fully automated production line, including Equipment Automation Programming (EAP), Automated Material Handling System (AMHS), and Standard Mechanical Interface (SMIF), has been established. Automation not only improves production efficiency and reduces human error but also further enhances product yield and reliability.

According to the foundry's data, the yield of J Square Semiconductor's foundry wafer products is approximately 5% higher than that of similar products from other customers of the same foundry.

Through these comprehensive optimization measures, J Square Semiconductor can not only achieve technological breakthroughs but also lay a solid foundation for the commercial application of SiC power chips.

Cost Drivers and Reduction Targets

To achieve a 50% cost reduction target from generation to generation, J Square Semiconductor has conducted in-depth analysis of key cost drivers in SiC MOSFET manufacturing and set clear reduction goals. These cost drivers primarily include:

• RSP (mOhm*Area): RSP (mOhm*Area) showed an actual reduction of 25% from G2 to G3, and a predicted average reduction range of 15% to 21% from G4 to G6, depending on the products, while carefully balancing all critical device factors such as BV, Critical Electric field, and mobility.
• Substrate: The 6-inch SiC P-grade substrate is currently one of the main cost contributors in SiC chip manufacturing. J Square Semiconductor aims for a Year-over-Year (YOY) reduction of 14% in substrate cost. This is attributed to the continuous maturation of manufacturing processes and yield enhancement.
• Epi: Epitaxial growth is another critical and costly step in SiC chip manufacturing. Through the maturation and innovative improvements in epitaxial processes, J Square Semiconductor has achieved an 11-15% YOY cost reduction, with further reductions expected in the next 1-2 years.
• Fab Manufacturing Cost: Wafer fabrication costs primarily stem from technology design and process integration optimization. J Square Semiconductor reduces costs by decreasing the number of masks (e.g., from an average of 12 to 10 for G3 products) and optimizing process ?ows, targeting a 5% YOY reduction, or 10% every two years.
• Packaging/FT: Packaging and Final Test (Packaging/FT) costs can be further reduced by 5% through higher yield per wafer and increased demand for high-volume production.

By effectively controlling and continuously optimizing these key cost drivers, J Square Semiconductor is con?dent in delivering products with double the value to end customers. This not only demonstrates its excellent capabilities in cost control but also lays an economic foundation for the widespread adoption of SiC technology.

Technical Innovation Improvements in Planar MOSFET

J Square Semiconductor has also made signi?cant progress in technical innovations for planar MOSFETs, which are crucial for enhancing device performance and reducing costs.

For G3, the mask count was reduced from an average of 12 to 10:

• Fine-tuned Cell Pitch Scaling: Through meticulous design and simulation, J Square Semiconductor has achieved cell pitch scaling from one generation to the next, allowing for the integration of more transistors within the same area and increasing current density. It also means the power module sizing can be scale down further for end users.
• Reduction of Source Contact Resistance (Rcs): Rcs has been effectively reduced without compromising its performance, which helps to lower the overall on-resistance of the device.
• Optimization of Channel Resistance (Rch): Reducing channel resistance is key to improving device performance. While lowering Rch, J Square Semiconductor fully considers Drain-Induced Barrier Lowering (DIBL), which lowers the threshold voltage (Vth) and increases off-state leakage.
• Improvement of SiO₂/SiC Interface States/Charge Traps: By optimizing interface characteristics, channel mobility is enhanced, and resistance is further reduced, thereby improving device efficiency and reliability.
• Shortening of JFET Region Length: Appropriately shortening the JFET region length helps reduce chip area. However, J Square Semiconductor emphasizes that this reduction must be kept within critical limits to avoid negative impacts on device performance.
• Optimization of Substrate Resistance (Rsub): Through wafer thinning technology, the Ron (on-resistance) margin is increased, further optimizing the overall performance of the device.

These technical innovations collectively drive J Square Semiconductor's leading position in the SiC MOSFET ?eld, enabling it to continuously provide high-performance, low-cost products.

J Square's Law vs. Normalized Cost Trend & Future Outlook

J Square Semiconductor's J Square’s Law has been implemented since 2023 and has achieved remarkable results. The company will continue to focus on technological innovation and collaborate closely with quali?ed substrate and epitaxial suppliers to further reduce costs and improve yield. This effort will continue until 2030, which is expected to be a signi?cant in?ection point - the transition from 6-inch to 8-inch SiC substrates.

Starting in 2026, J Square Semiconductor plans to apply J Square’s Law to the development of 8-inch SiC. This means that, under controllable costs, the company will be able to provide end customers with nearly double the chip volume. This strategy will continue until the 6-inch/8-inch substrate in?ection point, also expected prior to 2030. This forward-looking plan not only demonstrates J Square Semiconductor's clear vision in its technology road map but also heralds a more efficient and cost-effective era for the SiC power chip industry.

Conclusion

J Square's Law is a concentrated embodiment of J Square Semiconductor's continuous innovation and pursuit of excellence in the ?eld of Silicon Carbide power chips. By comprehensively optimizing on-resistance reduction, chip area reduction, yield and reliability improvement, and cost control, J Square Semiconductor has not only successfully enhanced the performance of SiC power chips but also signi?cantly reduced their manufacturing costs. This unique business model and technological strategy ensure that the company can continuously provide double the value to customers and maintain a leading position in the competitive market.

With the deepening implementation of J Square’s Law and the transition to 8-inch SiC substrates, J Square Semiconductor is expected to further solidify its leadership in the SiC power chip industry in the coming years and contribute signi?cantly to the green and e?cient development of the global power electronics industry. J Square's Law is not just a technological innovation; it is a business philosophy that will continue to drive the advancement of SiC technology and ultimately bene?t a wide range of end-users.

Note:

• J Square Semiconductor (Shanghai) Co., Ltd. successfully registered the "杰平方定律" ("J Square's Law") trademark in China in 2023.
• All rights reserved by J Square Semiconductor (Shanghai) Co., Ltd. This content is protected under the copyright laws of the People’s Republic of China and international copyright treaties and conventions. Any unauthorized reproduction, distribution, or use without prior written permission is strictly prohibited and may result in legal action in applicable jurisdictions.

責編：Johnson Zhang