【培訓(xùn)通知】高級數(shù)模轉(zhuǎn)換器（ADC）設(shè)計(jì)課程

通信、汽車、工業(yè)、醫(yī)療保健、云計(jì)算和人工智能等各個(gè)領(lǐng)域?qū)Ω邤?shù)據(jù)傳輸速率的需求不斷增長，推動(dòng)了具有更高分辨率的數(shù)十萬至數(shù)百億模數(shù)轉(zhuǎn)換器的持續(xù)研發(fā)。近年來，交錯(cuò)（TI）模數(shù)轉(zhuǎn)換器（ADC）經(jīng)歷了重大發(fā)展。SAR 型 ADC 滿足了 TI 和大規(guī)模 TI 子通道架構(gòu)的大部分要求。在過去二十年中，SAR ADC 不斷超越性能障礙，成為中低分辨率最節(jié)能的 ADC 拓?fù)洹Ｖ档米⒁獾氖牵ㄟ^采用純數(shù)字或模擬輔助校準(zhǔn)技術(shù)來解決 TI 實(shí)現(xiàn)中信道到信道的非理想性，從而提高了信號到噪聲失真（SNDR）性能。為了進(jìn)一步優(yōu)化速度、有效位數(shù)（ENOB）和功耗，SAR 和流水線拓?fù)涞幕旌辖M合得到了越來越多的應(yīng)用。功能擴(kuò)展促進(jìn)了緊湊型 TI SAR ADC 的發(fā)展，使其能夠?qū)崿F(xiàn)超過 100GSPS 的采樣率，成為大型片上系統(tǒng) (SoC) 集成的一部分。

本次課程首先深入探討大規(guī)模時(shí)間交織 ADC 的交織器拓?fù)浣Y(jié)構(gòu)，探討非理想情況、設(shè)計(jì)注意事項(xiàng)、建模技術(shù)和詳細(xì)案例研究。隨后，特別關(guān)注對高性能大規(guī)模 TI ADC 至關(guān)重要的外設(shè)塊的設(shè)計(jì)挑戰(zhàn)和解決方案，包括輸入緩沖器和參考緩沖器。此外，還研究了極限采樣器、殘差放大器和時(shí)鐘等關(guān)鍵 SAR ADC 塊，通過全面的案例研究介紹了基本概念和先進(jìn)技術(shù)。

The growing demand for higher data rates across various sectors such as communication, automotive, industrial, healthcare, cloud computing, and AI has driven the continuous research and development of multi-tens-of-giga to hundreds-of-giga ADCs with extended resolutions. Time-interleaved (TI) Analog-to-Digital Converters (ADCs) have undergone significant evolution in recent years. SAR-type ADCs have met most of the requirements for TI and Massive TI sub-channel architecture. Over the past two decades, SAR ADCs have consistently surpassed performance barriers, emerging as the most energy-efficient ADC topology for low to medium resolutions. Notably, improvements in Signal-to-Noise-Distortion (SNDR) performance have been achieved through the adoption of pure-digital or analog-assisted calibration techniques to address channel-to-channel non-idealities in TI implementations. Hybrid combinations of SAR and Pipeline topologies are increasingly utilized to optimize speed further, Effective-Number-Of-Bits (ENOBs), and power dissipation. Feature scaling has facilitated the development of compact TI SAR ADCs capable of achieving sampling rates beyond 100GSPS as part of large System-on-Chip (SoC) integration.?

The course begins by delving into interleaver topologies of massive time-interleaved ADCs, exploring non-idealities, design considerations, modeling techniques, and detailed case studies. Subsequently, specific attention is given to the design challenges and solutions of peripheral blocks crucial for high-performance massive TI ADCs, including the input buffer and reference buffer. Additionally, key SAR ADC blocks such as the extreme sampler, residue amplifier, and clocking are examined, covering fundamental concepts and advanced techniques through comprehensive case studies.

本課程的推薦目標(biāo)受眾是希望進(jìn)入ADC設(shè)計(jì)領(lǐng)域的模擬和混合信號設(shè)計(jì)工程師，以及已經(jīng)在使用 ADC 并有興趣學(xué)習(xí)先進(jìn)的超高速ADC設(shè)計(jì)技術(shù)的人員。希望掌握扎實(shí)ADC知識的高年級本科生或研究生。熟悉 ADC的基本概念會(huì)有幫助，但不是先決條件。

The recommended target audience for this course is analog and mixed-signal design engineers looking to get into ADC design as well as those already working with ADCs, and interested to learn advanced state-of-the-art ultra-high-speed ADC design techniques. Advanced undergraduate or graduate students who wish to develop a solid knowledge of ADC. Familiarity with fundamental ADC concepts will be beneficial but is not a pre-requisite.

上海林恩信息咨詢有限公司

上海集成電路技術(shù)與產(chǎn)業(yè)促進(jìn)中心

課程時(shí)間：2024年07月16日—17日（2天）

報(bào)到注冊時(shí)間：2024年07月16日，上午8:30-9:00

課程地點(diǎn)：上海集成電路技術(shù)與產(chǎn)業(yè)促進(jìn)中心（上海市浦東新區(qū)張東路1388號21幢）

課程注冊費(fèi)用：4600元/人；學(xué)生價(jià)：3600元/人；

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2024年07月16日—17日? （兩天）

Lecture 1:? Time Interleaver and Massive Time Interleaver (3 hours):

- Application and Technology Motivations

- Time-Interleaved Non-idealities

- Front-End Interleaver Topologies

- Topology Variety Considerations

- Modeling of Interleaver

- Uncertainties and Case Studies

Lecture 2: Wideband Input Buffer and Fast-transient Reference Buffer (2 hours)

- Input Network

- Nonlinearities

- Input Buffer Topologies

- Linearization Techniques

- Reference Ripple

- Reference Buffer Topologies

- Ripple Suppression Techniques

- Case Studies

Lecture #3 – Wideband Samplers (1 hour)

- Sampling Theory

- Sampler Non-idealities

- Bootstrapped Circuits

Lecture #4 – Clocking and Extreme Amplifier Overview (2 hours)

- Effect of Jitter on Sampling

- Low Jitter Clock Receivers

- Power Efficient and Low Jitter CMOS Clock Buffer

- Open-Loop Residue Amplifiers

- Close-Loop Residue Amplifiers

Lecture #5 – State-of-the-Art Low-Resolution High-Speed SAR ADCs (2 hours)

- Single-bit/cycle

- Multi-bit/cycle

- DAC Implementation

- SAR Loop

- SAR Switching Logic

- Redundancy

- Case Studies

Lecture #6 – Extended Resolution and High-Speed: Pipeline-SAR ADCs (2 hours)

- Fundamentals?

- Comparison with SAR ADCs

- Digital Error Correction

- Residue Amplification Errors

- Case Studies

Q&A: Related Problems faced by Participants