Dialog半導體公司近期有多個職位正在熱招中，我們期待優(yōu)秀的工程師朋友們加入我們的創(chuàng)新團隊！
如果您的技能、經(jīng)驗和意向與我們的職位契合，歡迎將您的簡歷發(fā)送至下列職位相應的郵箱。
郵箱投遞簡歷，郵件標題請注明：職位+地點+姓名+渠道（微信）
熱招職位列表
Senior Test Engineer (PCBU部門): 天津
Senior Test Technician (PCBU部門): 天津
Junior/Senior/Principal Digital Design Engineer (PCBU部門): 北京、天津、上海
Senior Digital Verification Engineer (PCBU部門): 北京、天津
Junior/Senior/Principal Analog Design Engineer (PCBU部門): 北京、天津、上海
Layout Engineer (PCBU部門): 北京、天津
(Senior) Layout Engineer (CMBU部門): 合肥
(Senior) Analog Design Engineer (CMBU部門): 合肥
Principal System & Applications Engineer (PCBU部門): 北京
System Engineering Manager (PCBU部門): 深圳
(Senior) Wi-Fi Application Software/Firmware Engineer (CAIBG部門): 上海
Senior/Principal Applications Engineer (DC-DC) (PCBU部門): 深圳
Senior/Principal Applications Engineer (Lighting) (PCBU部門): 深圳
以上職位的具體職能和要求詳情介紹如下：
1. Senior Test Engineer
地區(qū)：天津
部門：PCBU
職能：
Writing FPGA code in Verilog and user application library in C++.
Develop auto-test script with multiple programming language (C++ is a must) to meet requirement from IC design.
Maintaining a safe and high-efficient auto-test environment in manufacturing.
PCB design.
Verify and debug the test circuit.
Preparing reports on test results and data analysis.
Write document and provide training to test develop engineer.
Assisting in other test-related tasks such as reliability test and test processes review.
要求：
Bachelor’s Degree or above in Electrical Engineering, Computer Science or equivalent.
Engineering Degree or above in Electronics or equivalent education.
Minimum 5 years working experience of IC test development in Semiconductor company.
Minimum 2 years developing experience in FPGA system design and implementation.
Good analog and digital circuit design experience.
Proficiency in C/C++, Verilog.
Good experience in schematic entry and PCB layout.
Experience in working with international and cross-functional teams.
Fluent written and verbal English is essential.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
2. Senior Test Technician
地區(qū)：天津
部門：PCBU
職能：
Perform laboratory experiments and materials preparation following established procedures.
Report all testing results and provide preliminary analysis of the results for further improvement.
Follow all laboratory activities to security, safety & environment procedures & requirements.
Keep laboratory supplies ready by keeping stock of inventory, placing orders, and contacting with supply chain.
Support to train any junior technician or intern to perform ATE testing.
Verify incoming ATE HWs and identify problems with test results consulting with senior-level personal.
要求：
Engineering degree or above in Electronics or equivalent education.
Minimum 4 years work experience as lab test technician.
Good experience in ATE tester operation, such as ASL1K, ETS-88.
Computer skills on Microsoft word/excel/PowerPoint.
Strong/Fluent written & verbal English is essential.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
3. Junior/Senior/Principal Digital Design Engineer
地區(qū)：北京、天津、上海
部門：PCBU
職能：
Participate IP and chip level architecture definition, derive functional and design specifications and analyse feasibility of technical and architectures.
Implement design with Verilog to achieve specification goals. Simulate and debug the codes in the coding stage.
Go through the frontend design flow to deliver qualified netlist. Co-work with back-end team to fix timing issue and check floorplan.
Write ASIC specific part of test plan. Prove functional correctness from block level to top-level.
Design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, etc.)
Help other team members with technical training and coaching.
Work as the technical contact point on the ASIC area.
Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
要求：
PHD, MSEE or BSEE with digital IC design experience.
A minimum of 2-10 years digital design experience.
Strong RTL coding and familiar with front-end design flow.
Proven experience on synthesis, timing analysis and formal verification.
Be familiar with shell/perl/tcl programming in Linux OS.
Experience in mixed signal team is a plus; knowledge of analog design is a big plus.
Experience in power management chip design is a plus.
Experience in C/C++/SystemVerilog programming is a plus.
Good communication skills and fluent English.
Strong responsibilities and team spirit.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
4. Senior Digital Verification Engineer
地區(qū)：北京、天津
部門：PCBU
職能：
Participate IP and chip level architecture definition, derive functional and design specifications and analyse feasibility of technical and architectures.
Worked with design engineer to get a full deep insight on the design under test.
Develop stressful test plan and verification list.
Build testbench environment for block level and top-level.
Create testcases to ensure maximum coverage.
Make coverage analysis, and release verification report before tape-out.
Develop verification IP which can be reused at different levels of verification.
Maintain verification environment, solve flow issues, and develop scripts to improve flow efficiency.
要求：
Master level qualification in Electronics engineering or a related discipline typically required (but not mandatory).
3+ years’ experience with Master’s Degree or 5+ years’ experience with Bachelor’s Degree.
Strong system Verilog coding and familiar with digital verification flow based UVM.
Proven experience on digital verification projects.
Should be familiar with shell/Perl/TCL programming in Linux OS.
Experience in mixed signal team is a plus, knowledge of analog design is a big plus.
Experience in power management chip design is a plus.
Good communication skills and fluent English.
Strong responsibilities and team spirit.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
5. Junior/Senior/Principal Analog Design Engineer
地區(qū)：北京、天津、上海
部門：PCBU
職能：
Define power management system architecture and do system stability analysis.
Use different kinds of design tools to design and verify analog IC design on popular power processes.
Understand and verify any new manufacture process or flow.
Work closely with system/marketing teams to develop new project’s analog architecture. Convert marking/system requirements to analog design spec.
Work closely with digital design team on analog - digital interface definition and top-level verification.
Work closely with back-end designers to correctly implement analog designs to layout and do post-layout simulation.
Work closely with AE/ATE testing engineers at lab for chip debugging, testing and necessary customer supports.
Write block level design spec according to chip spec. Write design guide of block level. Prove owned design to satisfy the chip spec through checklist, simulation result in design review.
要求：
PHDEE or MSEE with analog IC design experience.
At least 3 -10years power management analog design experience, and a minimum of 5 years analog IC design experience with PHDEE or MSEE. ACDC experience is preference.
Analog chip production experience is preference.
Extensive experience in analog architecture, stability analysis and methodologies of power system, especially ACDC power system.
Familiar with all kinds of analog design EDA tools.
Fully understand popular power process for example UMC, TSMC, CSMC.
Good analog circuit design, analysis and debug skills.
Good documentation still.
Excellent interpersonal and communication skills, self-motivation and good team member.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
6. Layout Engineer
地區(qū)：北京、天津
部門：PCBU
職能：
Work closely with project leader and analog designers to design chip or block level layout on time.
Familiar with layout design and verification tools, understand existing and new manufacture process.
Fix and finish layout design related issues.
Take care of block level layout design from floor plan to physical verification.
Help front-end designer to do post layout parameter extraction, optimize the layout design with front-end design engineers.
Work with Sr. Layout designers to find or select the best solution when doing layout design.
要求：
BSEE above.
A minimum of 2 years analog IC layout design experience.
Familiar with layout design and verification tools and flow.
Have knowledge of layout techniques for matching, ESD, latch-up prevention and parasitic reduction.
Excellent interpersonal and communication skills, self-motivation and good team member.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
7. (Senior) Layout Engineer
地區(qū)：合肥
部門：CMBU
職能：
Full custom layout design in digital, analog, standard cells, IO pads, ESD structures from cell to top.
Contribute effectively as a team member or superior initiative & drive as a project lead.
Work closely with circuit engineers to implement their requirements & optimization into the layout.
Back-end verification including DRC, LVS, ERC.
Tape-out related activities following CAD flow.
Plan and scheduling the assigned layout schedule.
要求：
Above 2+ continuous years in IC layout design industry experience or equivalent related education.
Proficient in using layout tools: Cadence Virtuoso IC6.15/6.16/6.17 Layout L/XL/VXL.
Fluent in using verification tools: Cadence Assura. Mentor Calibre DRC & LVS.
Analog techniques & concepts of device match, electromigration, coupling, parasitic effects, Latch-up & quick layout size estimation.
Must equipped with organized concept of hierarchical layout floor planning based on schematics.
Requires to have strong schematic layout translation skill.
Strong debug & quick problem-solving skills for LVS, DRC & layout issues without much supervision.
Must be comfortable with fast paced environment.
Good communication skills.
Windows, Linux, Unix Operation System.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
8. (Senior) Analog Design Engineer
地區(qū)：合肥
部門：CMBU
職能：
Design of Analog and Mixed-Signal circuits, meeting their architectural requirements and specifications.
Contribute to the architectural definition of the design, and also to chip integration.
Perform the necessary calculations, design and verification simulations to ensure building blocks meet specifications, at the schematic level and after post layout extraction.
Work closely with Layout Designers to ensure the layout is completed properly, using all known methods.
Document for assigned blocks, test and characterization report, and hold preliminary/final design reviews.
Actively participate in the chip bring up, evaluation and characterization, with emphasis on owned blocks.
Address questions and issues related to his/her blocks raised by cross-functional personnel, such as Product, Characterization, Test, or Application Engineers.
Plan and scheduling the assignments and projects.
要求：
Above 2+ continuous years in IC layout design industry experience or equivalent related education.
Proficient in using layout tools: Cadence Virtuoso IC6.15/6.16/6.17 Layout L/XL/VXL.
Fluent in using verification tools: Cadence Assura. Mentor Calibre DRC & LVS.
Analog techniques & concepts of device match, electromigration, coupling, parasitic effects, Latch-up & quick layout size estimation.
Must equipped with organized concept of hierarchical layout floor planning based on schematics.
Requires to have strong schematic layout translation skill.
Strong debug & quick problem-solving skills for LVS, DRC & layout issues without much supervision.
Must be comfortable with fast paced environment.
Good communication skills.
Windows, Linux, Unix Operation System.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
9. Principal System & Applications Engineer
地區(qū)：北京
部門：PCBU
職能：
Support new product development (eg. Such as definition, new product/concept evaluation and so on).
Create demo boards, application note and worksheet.
Co-work with marketing team and promote new products.
Support FAEs (or customer) to solve various technical issue on application.
Provide technical supports (include dedicated board design) at key accounts directly.
Competitive analysis on technology and cost.
Be responsible for delivering training to FAE& customers & distributors where appropriate.
Provide feedback on new requirements for future products.
Taking public speaking opportunities at conferences/trainings where appropriate.
要求：
Master’s Degree or above. Degree (or equivalent) in Electronic Engineering (or relevant discipline).
Minimum of 8+ (3+ with Ph.D. degree) years’ experience on power supply design or application.
Strong oral/written English.
Strong communication/interpersonal skills.
Relevant Hardware/SW experience in design environment as per job specification.
Excellent communication skills with ability to articulate complex technical subjects in a confident and clear way.
Fluent in English.
Strong customer facing skills.
Confident when speaking in public (training, seminars etc.).
May take additional responsibilities.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
10. System Engineering Manager
地區(qū)：深圳
部門：PCBU
職能：
Responsible for the growth and expansion of Renesas AMSBG BU SSL IC.
Providing direction and support to the sales and AE on new and current SSL products, especially on Commercial lighting segment, Knowledge in DALI is preferred.
Monitoring and driving key customer opportunities to ensure success.
Interfacing with the Applications groups to develop design collateral and promotional platforms.
Understanding competitive product/technology threats to form defensive product strategies.
Understanding customer/market requirements and opportunities for new products/packages through customer visits.
要求：
A minimum of 5 years of experience in technical marketing or applications in AC-DC or DC-DC power conversion semiconductors, experience in Lighting market is preferred.
Exceptional written and verbal communication skills including customer presentations.
Bachelor or higher degree in electronics engineering or related major.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
11. (Senior) Wi-Fi Application Software/Firmware Engineer
地區(qū)：上海
部門：CAIBG
職能：
The candidate will function as a Wi-Fi Application Software/Firmware Engineer developing and supporting supper low power Wi-Fi products. Specific duties include but not limited to:
Provide design, development, and debug support for complete customer product development cycle from product definition to production line test.
Ability to provide deep level hands-on Wi-Fi software/firmware customer support in elements such as debugging, code porting, code optimisation, peripheral utilization and help customer fix issues and then move to mass production.
Customising reference designs from the Business unit to local customer needs.
Work closely with sales team, FAE, and customers to adapt Dialog technologies to new platforms and solutions.
Providing feedback to the product line on suggestions to improve deliverables: tools / device / architecture / reference designs.
Some on-site customer travel will be required.
要求：
Graduate from Science Course with Bachelor Degree.
Knowledge, Skills and Experience:
BSEE/BSCS or MSEE/MSCS, 3 - 10 years of embedded software/firmware development experience using C/C++ programming languages.
Familiar with RTOS and Linux architectures, Linux Driver development is a strong plus.
Have a good technical understanding of Wi-Fi System.
Good understanding about WLAN spec and protocol.
Experienced in Wi-Fi software stack development and debugging - device driver, kernel networking stacks, firmware.
Good at Packet analysis - MAC and TCP/IP level with Wireshark/OmniPeek tools.
Familiar with Arm Cortex M and connectivity interface: I2C, SPI, UART, SDIO, USB etc.
Team player.
Good interpersonal communication and writing skills in English.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
12. Senior/Principal Applications Engineer (DC-DC)
地區(qū)：深圳
部門：PCBU
職能：
Support new product development (eg. Such as definition, new product/concept evaluation and so on).
Create demo boards, application note and worksheet.
Co-work with marketing team and promote new products.
Support FAEs (or customer) to solve various technical issue on application.
Provide technical supports (include dedicated board design) at key accounts directly.
Competitive analysis on technology and cost.
Be responsible for delivering training to FAE& customers & distributors where appropriate.
Provide feedback on new requirements for future products.
Taking public speaking opportunities at conferences/trainings where appropriate.
要求：
Minimum of 8+ (3+ with Ph.D. Degree) years’ experience on Power Supply Design or Application.
Degree (or equivalent) in Electronic Engineering (or relevant discipline). Master’s Degree or above.
Relevant Hardware/SW experience in design environment as per job specification.
Excellent communication skills with ability to articulate complex technical subjects in a confident and clear way.
Strong customer facing skills.
Confident when speaking in public (training, seminars etc.).
May take additional responsibilities.
Strong oral/written English.
Strong communication/interpersonal skills.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
13. Senior/Principal Applications Engineer (Lighting)
地區(qū)：深圳
部門：PCBU
職能：
Support new product development (eg. Such as definition, new product/concept evaluation and so on).
Create demo boards, application note and worksheet.
Co-work with marketing team and promote new products.
Support FAEs (or customer) to solve various technical issue on application.
Provide technical supports (include dedicated board design) at key accounts directly.
Competitive analysis on technology and cost.
Be responsible for delivering training to FAE& customers & distributors where appropriate.
Provide feedback on new requirements for future products.
Taking public speaking opportunities at conferences/trainings where appropriate.
要求：
Minimum of 8+ (3+ with Ph.D. Degree) years’ experience on Power Supply Design or Application.
Degree (or equivalent) in Electronic Engineering (or relevant discipline). Master’s Degree or above.
Relevant Hardware/SW experience in design environment as per job specification.
Excellent communication skills with ability to articulate complex technical subjects in a confident and clear way.
Strong customer facing skills.
Confident when speaking in public (training, seminars etc.).
May take additional responsibilities.
Strong oral/written English.
Strong communication/interpersonal skills.
請發(fā)送簡歷至：sophie.fang@diasemi.com 以及 quinee.xu@diasemi.com
關于Dialog半導體公司
Dialog半導體公司（瑞薩電子全資子公司）是推動物聯(lián)網(wǎng)和工業(yè)4.0應用發(fā)展的標準化和定制集成電路（IC）領先供應商。Dialog提供電池管理、低功耗藍牙（BLE）、Wi-Fi、閃存、可配置混合信號IC等經(jīng)市場驗證的產(chǎn)品技術，助力客戶的下一代產(chǎn)品開發(fā)，提升功率效率、縮短充電時間，并不斷提高性能和生產(chǎn)效率。
憑借數(shù)十年的技術經(jīng)驗和世界領先的創(chuàng)新實力，我們幫助設備制造商引領未來。我們對技術創(chuàng)新的熱情和創(chuàng)業(yè)精神使我們始終在高能效半導體技術領域保持領先地位，助力物聯(lián)網(wǎng)、移動設備、計算和存儲、智慧醫(yī)療和汽車市場的發(fā)展。2020年，Dialog實現(xiàn)了13.76億美元營業(yè)收入。目前，公司在全球約有2300名員工。
