我們在用verilog或VHDL設計數字系統時，通常有行為描述和結構描述等多種表述方式，你寫的verilog或VHDL源碼都會被綜合器軟件轉化為RTL級描述，而RTL級描述也是用verilog或VHDL語言來表述的，行為描述和結構描述,RTL級描述都是用verilog或VHDL語言來表述的，那么到底什么是硬件描述語言的RTL描述？或者它們有啥差別，還需要綜合器費盡心思做這樣的轉換？
簡單說，RTL描述就是用組合電路構成的數據通路+觸發器的方式來等效描述你的原始設計，下圖所示就是一個簡單示意，觸發器的輸入只有數據通路的輸出：
這種等效的描述轉化，將復雜的數字系統邏輯結構歸一化了，分為兩類：組合電路構成的數據路徑和觸發器鎖存，有點大家在數字電路課程里講組合邏輯化簡時，我們首先把邏輯表達式化為統一的最小項表達式，然后再在最小項表達式基礎上做更多的其他工作，道理類似，一種統一的、一致性的、甚至可能是唯一的表述方式，更利于后續工作，這種RTL描述有很多好處：
“Many optimizations and analyses can be performed best at the RTL level. Examples include FSM detection and optimization, identification of memories or other larger building blocks and identification of shareable resources.”
“Note that RTL is the fifirst abstraction level in which the circuit is represented as a graph of circuit elements(registers and combinatorial cells) and signals. Such a graph, when encoded as list of cells and connections,is called a netlist.RTL synthesis is easy as each circuit node element in the netlist can simply be replaced with an equivalentgate-level circuit. However, usually the term RTL synthesis does not only refer to synthesizing an RTLnetlist to a gate level netlist but also to performing a number of highly sophisticated optimizations withinthe RTL representation, such as the examples listed above. ”
這是做邏輯庫映射和布局布線的基礎，當然這種轉換后要保持原邏輯等效，FPGA的綜合器干得就是這活。
